Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver

ABSTRACT

A digital television (DTV) transmitter and a method of processing data in the DTV transmitter are disclosed. A pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and for inserting known data to at least one of the enhanced data packets. A first multiplexer multiplexes the enhanced data packets with main data packets including the main data. An RS encoder RS-codes the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity place holders to each enhanced data packet. And, a data interleaver interleaves the RS-coded main and enhanced data packets, wherein a known data sequence is included in every Nth enhanced data segment outputted from the data interleaver.

This application claims the benefit of the Korean Patent Application No. 10-2005-0132489, filed on Dec. 28, 2005, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital communication system, and more particularly, to a digital television (DTV) transmitter/receiver and a method of processing data in the DTV transmitter/receiver. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for transmitting and receiving digital broadcasts.

2. Discussion of the Related Art

Generally, the 8T-VSB transmission system adopted as a digital broadcasting standard by Korea and North America is a digital broadcast system developed for MPEG video/audio data transmission.

As the digital signal processing technology rapidly develops with the global use of Internet, the tendency for combining digital home appliances, computer and Internet together rises. So, in order to meet the user's various demands, many efforts need to be made to develop a system capable of transmitting various additional data with video/audio data.

A user of additional data broadcasting is expected to use the additional data broadcasting using a PC card or portable device having a simple type indoor antenna attached thereto.

Yet, signal intensity can be considerably decreased due to a shield effect of a wall and an influence of a near moving object within an indoor space and broadcast receiving performance can be reduced due to a ghost and noise generated from a reflective wave. Unlike a case of general video/audio data, a case of additional data transmission should have a lower error rate. In case of the video/audio data, an error failing to be detected by human eyes/ears does not matter. Yet, in case of additional data (e.g., a program execution file, stock information, etc.), a 1-bit error can cause a serious problem. So, the demand for developing a system more persistent against ghost and noise generated from a channel rises.

Additional data transmission will be performed by time-division through the same channel of MPEG video/audio in general. Since the beginning of digital broadcasting, ATSC VSB digital broadcast receivers receiving the MPEG video/audio only have globally spread in markets. So, the additional data transmitted on the same channel of the MPEG video/audio should avoid causing any effect to the conventional ATSC VSB dedicated receiver previously supplied to the markets. Such a situation is defined as ATSC VSB compatibility. And, an additional data broadcast system should be compatible with the ATSC VSB system. Besides, the additional data could be called enhanced data or E-VSB data.

However, in a poor channel environment, reception performance of the conventional ATSC VSB reception system may be reduced. Specifically, a portable or mobile receiver needs higher robustness against a channel change and noise.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a digital television (DTV) transmitter and a method of coding main and enhanced data in the DTV transmitter that substantially obviate one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a digital television (DTV) transmitter and a method of coding main and enhanced data in the DTV transmitter, by which a new digital broadcast system suitable for additional data transmission and robust against noise can be provided.

Another object of the present invention is to provide a digital television (DTV) transmitter and a method of coding main and enhanced data in the DTV transmitter, by which reception performance can be enhanced by transmitting known data known by a transmitting/receiving side in a manner of inserting the known data in a prescribed area of a data section.

A further object of the present invention is to provide a digital television (DTV) transmitter and a method of coding main and enhanced data in the DTV transmitter, by which known data insertion is efficiently facilitated in a manner of performing non-systematic RS encoding on enhanced data including known data.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a digital television (DTV) transmitter for coding main and enhanced data for transmission includes a pre-processor for pre-processing the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data, a data formatter for generating enhanced data packets including the pre-processed enhanced data and for inserting known data to at least one of the enhanced data packets, a first multiplexer for multiplexing the enhanced data packets with main data packets including the main data, an RS encoder for RS-coding the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity place holders to each enhanced data packet, and a data interleaver for interleaving the RS-coded main and enhanced data packets, wherein a known data sequence is periodically included in the interleaved data packets. Herein, the RS encoder may insert non-systematic RS parity data into the RS parity place holders included in each enhanced data packet. The RS encoder may also insert null data into the RS parity place holders included in each enhanced data packet.

The DTV transmitter may further include a byte-symbol converter for converting the interleaved data packets into symbols, and a trellis encoder for trellis-encoding the converted symbols, the trellis encoder being initialized when the symbols outputted from the byte-symbol converter represent a beginning of the known data sequence. Herein, the DTV transmitter may further include an initialization controller for generating initialization data symbols required to initialize one or more memories included in the trellis encoder, and a second multiplexer for outputting the initialization data symbols to the trellis encoder when the symbols outputted from the byte-symbol converter represent the beginning of the known data sequence. Additionally, the DTV transmitter may further include a backward-compatibility processor for generating new parity symbols based on an output of the RS encoder and the initialization data symbols and providing the new parity symbols to the second multiplexer. Herein, the second multiplexer may output the new parity symbols to the trellis encoder when the symbols outputted from the byte-symbol converter represent the RS parity place holders. And the initialization controller may generate the initialization data symbols based on previous values of the memories such that current values of the memories are set to zero.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:

FIG. 1 is a block diagram of a digital broadcast transmitting system according to one embodiment of the present invention;

FIG. 2 is a block diagram of a trellis encoding unit of the digital broadcast transmitting system shown in FIG. 1;

FIG. 3 is a diagram of a data interleaver shown in FIG. 2;

FIG. 4 is a diagram for explaining an output sequence of a data interleaver on a VSB frame;

FIG. 5 is diagram of data configurations of input and output ends of a data interleaver according to known data insertion of the present invention;

FIGS. 6A to 6C are diagrams of data configurations in byte and symbol domains of input and output ends of a data interleaver according to the present invention, in which known data are inserted by 4-data segment period;

FIGS. 7A to 7C are diagrams of data configurations in byte and symbol domains of input and output ends of a data interleaver according to the present invention, in which known data are inserted by 5-data segment period;

FIGS. 8A to 8C are diagrams of data configurations in byte and symbol domains of input and output ends of a data interleaver according to the present invention, in which known data are inserted by 8-data segment period; and

FIG. 9 is a block diagram of a digital broadcast receiving system according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

In the present invention, enhanced data can correspond to such data having information such as a program execution file, stock information and the like or may correspond to video/audio data. And, known data is the data previously known by agreement between transmitting and receiving sides. Moreover, main data is the data receivable by a conventional receiving system and includes video/audio data.

The present invention enhances reception performance of a receiver in a manner of multiplexing enhanced data and known data known by a transmitting/receiving side and transmitting the multiplexed data.

In particular, by performing non-systematic RS encoding on enhanced data including known data, the present invention enables a repetitive long known data sequence to be inserted and raises a degree of freedom for an insertion place.

FIG. 1 is a block diagram of a digital broadcast transmitting system according to one embodiment of the present invention.

Referring to FIG. 1, a digital broadcast transmitting system according to one embodiment of the present invention includes an E-VSB pre-processor 101, an E-VSB packet formatter 102, a packet multiplexer 103, a data randomizer 104, a scheduler 105, an E-VSB post-processor 110, an RS (Read-Solomon) encoder & non-systematic RS parity holder inserter 121, a data interleaver 122, a trellis encoding unit 123, a backward-compatibility processor 130, a frame multiplexer 140 and a transmitter 150.

In the above-configured transmitting system, main data is outputted to the packet multiplexer 103 by transport packet unit, whereas enhanced data is outputted to the E-VSB pre-processor 101.

The E-VSB pre-processor 101 performs pre-processing such as additional error correction encoding, interleaving, null data insertion and the like on the enhanced data and then outputs the pre-processed data to the E-VSB packet formatter 102.

The E-VSB packet formatter 102 configures a group by multiplexing the pre-processed enhanced data and previously defined known data or a known data place holder together under the control of the scheduler 105. The E-VSB packet formatter 102 divides data within the group into 184-byte enhanced data packets, attaches a 4-byte MPEG header to a front of each of the packets and then outputs a 188-byte enhanced data packet (i.e., MPEG compatible packet). In particular, one enhanced data packet group includes a plurality of consecutive enhanced data packets. An insertion place of the known data will be explained in detail later.

An output of the E-VSB packet formatter 102 is inputted to the packet multiplexer 103. The packet multiplexer 103 performs time division multiplexing on the 188-byte main data packet and the 188-byte enhanced data packet by transport stream (TS) packet unit to output under the control of the scheduler 105.

In particular, the scheduler 105 generates a control signal enabling the packet multiplexer 103 to multiplex the main and enhanced data packets together and then outputs the control signal to the packet multiplexer 103. If so, the packet multiplexer 103 having received the control signal multiplexes the main data packet and the enhanced data packet into the TS packet unit to output.

An output of the packet multiplexer 103 is inputted to the data randomizer 104. The data randomizer 104 removes MPEG sync byte from an input packet, randomizes the rest 187 bytes using an internally generated pseudo-random byte and then outputs the randomized packet to the E-VSB post-processor 110.

The E-VSB post processor 110 includes an RS encoder & non-systematic parity place holder inserter 111, a data interleaver 112, an E-VSB convolutional coder 113, a data interleaver 114 and an RS byte remover 115.

The RS encoder & non-systematic parity place holder inserter 111 of the E-VSB post-processor 110 performs systematic RS encoding or non-systematic parity place holder insertion on the randomized data.

In particular, if a 187-byte packet outputted from the data randomizer 104 is a main data packet, the RS encoder & non-systematic parity place holder inserter 111 attaches a 20-byte parity byte to a rear of the 187-byte data by performing systematic RX encoding like the conventional ATSC VSB system and then outputs the attached data to the data interleaver 112.

Meanwhile, if a 187-byte packet outputted from the data randomizer 104 is an enhanced data packet, the RS encoder & non-systematic parity place holder inserter 111 determines a 20-parity byte place within the packet, inserts a null byte in the determined parity byte place, sequentially inserts bytes of the enhanced data packet in the rest of 187 byte places and then outputs them to the data interleaver 112.

In this case, the place of the RS parity byte corresponds to a parity place in a non-systematic RS encoder and may differ for each enhanced data packet. This is because a place where known data (or known data place holder) is inserted can differ for each enhanced data packet. And, a known data place holder to initialize a memory of a trellis encoder can be inserted. If the known data place holder is inserted, its place may differ.

In this case, the place of the RS parity byte should be placed in a manner that the RS parity place holder bytes are outputted behind the known data for initialization (or known data place holder for initialization) at the data interleaver.

In particular, the position of the known data (or known data place holder) used in initializing the trellis encoder should be determined to be outputted ahead of the RS parity byte place from the data interleaver output end.

In other words, the known data (or known data place holder) used in initializing the trellis encoder needs to be outputted earlier than the RS parity place holder at the output end of the data interleaver. Yet, the rest of the known data (or known data place holder) unused in initializing the trellis encoder can be outputted behind or ahead of the RS parity place holder.

The data interleaver 112 performs data interleaving on an output of the RS encoder & non-systematic parity place holder inserter 111 and then outputs it to the E-VSB convolutional coder 113. A data interleaving operation of the data interleaver 112 will be explained in detail later.

The E-VSB convolutional coder 113 performs convolutional coding on an output of the data interleaver 112 and then outputs it to the data deinterleaver 114.

The data deinterleaver 114 performs data deinterleaving on input data by a reverse process of the data interleaver 112 and then outputs the deinterleaved data to the RS byte remover 115.

The RS byte remover 115 removes the 20-byte parity attached by the RS encoder & non-systematic parity place holder inserter 111. In this case, if the inputted data is the main data packet, the RS byte remover removes last 20 bytes from 207 bytes. IF the inputted data is the enhanced data packet, the RS byte remover 115 removes 20-byte RS parity place holder from 207 bytes. This is to re-calculate parities since original data is modified by the E-VSB convolutional coder 113 in case of the enhanced data.

The E-VSB convolutional coder 113 converts inputted bytes to symbols, performs convolutional coding on an enhanced data symbol only, converts the coded result to bytes, and then outputs the converted bytes. In particular, the E-VSB convolutional coder 113 outputs data without modification if an output of the data interleaver 112 is the main data, the MPEG header byte attached by the E-VSB packet formatter 102 or the RS parity byte or parity place holder byte attached to the enhanced data packet by the RS encoder & non-systematic RS parity place holder inserter 111.

Meanwhile, the known data can be inserted in the enhanced data packet by the E-VSB packet formatter 102. Alternatively, the E-VSB packet formatter 102 inserts a place holder of the known data and the E-VSB convolutional coder 113 inserts the known data in the corresponding place instead of the place holder. And, the E-VSB convolutional coder 113 outputs the known data symbol without additional coding like the main data.

An output of the RS byte remover 115 is inputted to the RS encoder & non-systematic RS parity place holder inserter 121.

Like the former RS encoder & non-systematic RS parity place holder inserter 111, if a 187-byte packet outputted from the RS byte remover 115 is a main data packet, the RS encoder & non-systematic RS parity place holder inserter 121 attaches 20-byte parity bytes to a rear of 187-byte data by performing systematic RS encoding in the same manner of the conventional ATSC VSB system. In case of an enhanced data packet, a 20-parity byte place is determined and it is able to insert RS parity obtained by performing non-systematic RS encoding in the determined parity byte place or to insert null byte (i.e., RS parity place holder) therein instead of the RS parity. And, bytes within the enhanced data packet are sequentially inserted in the rest 187 byte places among 207 byte places. The null byte can be set to an arbitrary value and is replaced by a parity value calculated by a non-systematic RS encoder 133 of the backward-compatibility processor 130. Hence, the null byte plays a role in holding a place of the parity byte of a non-systematic RS code.

An output of the RS encoder and non-systematic RS parity place holder inserter 121 is outputted to the data interleaver 122 and also inputted to a backward-compatibility processor 130 to re-calculate parity in case of the enhanced data packet.

Besides, the data interleaver 122 performs interleaving on input data according to the same interleaving rule of the former data interleaver 112.

FIG. 3 is a diagram of the data interleaver (122 or 112) shown in FIG. 2, in which a convolutional interleaver is exemplarily shown. In this case, the number of branches is 52 and the number (M) of unit memory bytes is 4 (M=4).

Referring to FIG. 3, in the data interleaver, if a first byte is inputted, it is directly outputted via a first branch. A second byte is inputted via a second branch, by which a value prior to 52*4 byte is outputted.

FIG. 4 is a diagram for explaining input and output sequences of a data interleaver on a VSB frame.

Referring to FIG. 4, data inputs are sequentially inputted by segment unit from top to bottom. And, bytes within a segment are sequentially inputted left to right. Numerals in the drawing indicate output sequences of a data interleaver. In this case, the data interleaver operates by 52-segment unit.

An output of the data interleaver 122 is inputted to the trellis encoding unit 123. And, the trellis encoding unit 123 encodes a 2-bit input into three bits to output.

An output of the trellis encoding unit 123 is inputted to the frame multiplexer 140.

The frame multiplexer 140 inserts a field sync and a segment sync in the output of the trellis encoding unit 123 and then outputs a corresponding signal to the transmitter 150.

The transmitter 150 includes a pilot inserter 151, a VSB modulator 152 and a radio frequency (RF) converter 153. And, the transmitter 150 plays the same role of the conventional VSB transmitter.

To make the output data of the trellis encoding unit 123 into known data defined by a transmitting/receiving side, initialization of a memory within the trellis encoding unit 123 is needed for the known data inserted in the enhanced data packet.

For the initialization, an input of the trellis encoder needs to be modified. And, RS parity affected by the correspondingly modified data is re-calculated to be substituted for original parity data. This process is performed by the backward-compatibility processor 130.

FIG. 2 is a detailed diagram of the trellis encoding unit 123 that can be initialized.

Referring to FIG. 2, a trellis encoding unit according to one embodiment of the present invention includes a byte-to-symbol converter 201, a multiplexer 202 selecting a trellis encoder input, a trellis encoder 203 and an initialization controller 204 initializing the trellis encoder.

The byte-to-symbol converter 201 of the trellis encoder unit receives data-interleaved data by byte unit, converts the received data to symbol unit, performs 12-way interleaving, and then outputs the interleaved data to the multiplexer 202.

In general, an output of the byte-to-symbol converter 201 is selected by the multiplexer 202 and is then directly outputted to the trellis encoder 203. Yet, if the interleaved data is known data and if the known data corresponds to a beginning part of a known data sequence consecutively inputted, initialization of the trellis encoder 203 is necessary. The trellis encoder 203 includes a memory and a current output is affected by a current and previous inputs. So, in order to output a known data pattern after trellis encoding, a process for initializing the memory within the trellis encoder 203 to a predetermined value is needed.

In case that the initialization of the memory of the trellis encoder 203 is needed, a portion of the known data is replaced by initialization data to be outputted to the trellis encoder 203. If so, the memory within the trellis encoder 203 is initialized to a predetermined value by the initialization data. An output of the trellis encoder 203 after the initialization can become the known data encoded into a pattern promised by the transmitting/receiving side.

The initialization controller 204 initializing the trellis encoder 203 receives a value of the memory within the trellis encoder 203, generates initialization data to be inputted to the trellis encoder 203, and then outputs the generated data to the multiplexer 202 and the backward-compatibility processor 130.

In particular, the trellis encoder 203 encodes an upper bit of two bits configuring one symbol into 1 bit using one memory and then outputs the 1 bit. And, the trellis encoder 203 encodes a lower bit of the two bits into 2 bits using two memories and then outputs the 2 bits. In this case, if input data is the known data and if the known data corresponds to a beginning part of a consecutively inputted known data sequence, the memories need to be initialized to output specific known data after trellis encoding.

So, if the initialization of the memory within the trellis encoder 203 is needed, the initialization controller 204 generates initialization data according to a current state and specific initialization state of the memory and then outputs the generated initialization data to the multiplexer 202.

The initialization data consists of 4 bits, i.e., two symbols. In this case, the trellis encoder 203 includes twelve encoders. And, twelve bytes outputted from the multiplexer 202 are sequentially inputted to the twelve encoders, respectively. In this case, initial four bits, i.e., two symbols of each byte can become the initialization data. In particular, the initialization controller 204 generates initialization data for initializing the memory of the trellis encoder 203 in the two symbol sections from which a known data sequence starts and then outputs the generated initialization data to the multiplexer 202 and the backward-compatibility processor 130.

The backward-compatibility processor 130 receives the output of the RS encoder & non-systematic parity place holder inserter 121 and the output of the initialization controller 204 of the trellis encoding unit 123, generates non-systematic 20-byte parity and then outputs the generated parity to the multiplexer 202 of the trellis encoding unit 123.

In particular, since the initialization for the memory of the trellis encoding unit 123 is achieved by new data instead of being achieved by the data interleaved by the data interleaver 122, the RS parity is re-generated to be substituted for original parity data. And, this is performed by the backward-compatibility processor 130.

The backward-compatibility processor 130 includes a packet buffer 131, a symbol-to-byte converter 132, a non-systematic RS encoder 133 and a byte-to-symbol converter 134.

The output of the RS encoder & non-systematic RS parity place holder inserter 121 is inputted to the data interleaver 122 and the packet buffer 131 of the backward-compatibility processor 130. And, the initialization data of the initialization controller 204 of the trellis encoding unit 123 is inputted to the multiplexer 202 of the trellis encoding unit 123 and the symbol-to-byte converter 132 of the backward-compatibility processor 130.

In this case, since the input and output of the RS encoder and non-systematic RS parity place holder inserter 121 follow byte units, the symbol-to-byte converter 132 converts the symbol unit of the initialization data to the byte unit and then outputs the converted data to the packet buffer 131.

The packet buffer 131 receives a byte output of the RS encoder and non-systematic RS parity place holder inserter 121 and a byte output of the symbol-to-byte converter 132, temporarily stores the received outputs and then outputs the stored outputs to the non-systematic RS encoder 133.

The non-systematic RS encoder 133 receives a byte output of the packet buffer 131, generates 20-byte parity and then outputs the generated parity to the multiplexer 202 of the trellis encoder 13 via the byte-to-symbol converter 134 for the unit conversion to the symbol unit.

If the inputted data, which was interleaved and converted to the symbol, corresponds to the beginning part of the known data sequence, the multiplexer 202 selects to output an initialization symbol of the initialization controller 204 instead of the inputted symbol. If the inputted data is a parity place holder, the multiplexer 202 selects an output symbol of the symbol-to-byte converter 134 of the backward-compatibility processor 130 instead of the inputted symbol. In other cases, the multiplexer 202 selects the inputted data from the byte-symbol converter 201, which was interleaved and converted to the symbol, and then outputs the selected data to the trellis encoder 203.

In particular, symbols at the first two places of the known data sequence are substituted by the initialization symbols to be inputted to the trellis encoder 203. A symbol at a parity place within each packet is substituted by the parity symbol re-calculated by the backward-compatibility processor 130 to be inputted to the trellis encoder 203. In case that the RS encoder & non-systematic RS parity place holder inserter 121 inserts a null byte for the enhanced data packet instead of inserting a non-systematic RS parity, a non-systematic RS parity of the enhanced data packet is calculated by the backward-compatibility processor 130 regardless of the initialization of the trellis encoder to be substituted for the null byte and is then inputted to the trellis encoder 203.

The trellis encoder 203 performs trellis encoding on the data outputted from the multiplexer 202 and then outputs the encoded data to the frame multiplexer 140. And, the trellis encoder 203 outputs a state of the memory within the trellis encoder to the initialization controller 204.

Known Data Insertion and Non-Systematic RS Parity Place

Known data insertion and non-systematic RS parity place Setting according to the present invention are explained in detail as follows.

First of all, if an inputted 187-byte packet is a main data packet, the RS encoder & non-systematic RS parity place holder inserter generates 20-byte parity by performing systematic RS encoding like the ATSC VSB system and then attaches the generated 20-byte parity to a rear of the 187-byte.

In case of an enhanced data packet, 187 bytes among 207 bytes to be outputted correspond to the inputted data and 20 bytes become a parity byte. This is the same case of the systematic RS encoding. Yet, a place of the 20-byte parity may differ within 207 bytes for each enhanced data packet and a parity value is found by non-systematic RS encoding.

Once the parity place is determined, data is placed at 187 bytes where the parity is not located.

Non-systematic parities inserted by the RS encoder & non-systematic RS parity place holder inserter may become practical parties or just correspond to a meaningless byte for holding the parity place. In case that the non-systematic RS parities are inserted as the meaningless byte, the backward-compatibility processor calculates the parity value for substitution.

The RS parity is re-calculated by the backward-compatibility processor for the enhanced data packet including the trellis initialization data, of which reason is explained as follows.

For an enhanced data packet that includes a known data to be replaced by the trellis initialization data, it is required to re-calculate the RS parity data for the enhanced data packet since the replacement by the initialization data is performed in the trellis encoding unit 123 which is behind the RS encoder or non-systematic RS parity place holder inserter 121.

In other words, if a place of a parity existing within one packet comes behind the data to be substituted by initialization at an input of the trellis encoder, it is able to calculate a new parity by RS encoding by using the substituted data. In this case, if systematic RS encoding is performed on the enhanced data packet including the initialization data, it is unable to insert known data in a parity area since the RS parity place is already determined. And, a place of data coming ahead of the parity is very limited. So, an area available for trellis initialization is correspondingly limited.

Yet, if the non-systematic RS encoding is performed on the enhanced data packet including the initialization data, the parity place is movable and the known data can be inserted in the parity area of the systematic RS encoding. And, it is also advantageous that the limitation of the data place for the trellis initialization is almost eliminated as compared with the case of using the systematic RS encoder.

Yet, the known data (or known data place holder) used for the initialization of the trellis encoder should be inputted to the trellis encoding unit 123 ahead of the RS parity place holder.

If one packet is inputted to the data interleaver shown in FIG. 3, it is interleaved and outputted by byte unit. The interleaving does re-ordering of data sequence.

FIG. 4 is a diagram for explaining input/output order of a data interleaver on a VS frame.

Referring to FIG. 4, data within a packet is inputted to the data interleaver by byte unit. In this case, the data is inputted top to bottom according to a segment sequence. And, the data in inputted from a left first byte to a right 207^(th) byte in order within a segment.

Thus, if the data is inputted and if an n^(th) field starts in FIG. 4, a data interleaver input is carried out in a sequence of byte #1, byte #210 and the like. And, a data interleaver output is carried out in a sequence of byte #1, byte #2, byte #3 and the like. Hence, the sequence of the inputted bytes and the sequence of the outputted bytes are different from each other by interleaving.

In particular, since the data interleaver has the configuration of the convolutional interleaver having the branch (B) of 52, the sequence, as shown in FIG. 4, goes round by a 52-byte cycle in outputting one segment. Hence, byte #210, byte #262 and the like are outputted after byte #1, byte #53, byte #105 and byte #157 have been outputted.

So, if the systematic RS encoding is to be performed, RS parity should exist at last 20 bytes of each segment. And, RS parities can be outputted according to the interleaved output sequence ahead of the initialization bytes for the trellis initialization for the known data generation.

If so, RS encoding should be performed ahead of information indicating how data should be substituted for the initialization. Yet, this is impossible. So, error takes place in RS decoding.

In aspect of one segment unit for the data interleaver output, each segment can be configured in a manner that substitution data for initialization is located at a place of data outputted ahead of all systematic RS parity bytes. Yet, places of initialization bytes are restricted to limited area, and thus this to put limitation on an area in which known data can be inserted.

Yet, as mentioned in the foregoing description, in aspect of a place of RS parity within one segment and in aspect of an output of the data interleaver, the restriction, which occurs in case of using the systematic RS encoding only, for the known data insertion place can be eliminated only if parity is calculated by enabling the RS parity to be outputted behind the initialization bytes and by performing the non-systematic RS encoding. And, compatibility with the conventional VSB receiver incapable of supporting E-VSB can be maintained as well.

FIG. 5 is diagram of data configurations before and after a data interleaver according to known data insertion of the present invention.

In FIG. 5A, a data configuration at an input end of a data interleaver is shown. And, a configuration at an output end of the data interleaver corresponding to the input configuration of FIG. 5A is shown in FIG. 5B.

First of all, a receiver receives data in an order of a data interleaver output end. To receive consecutive known data, known data should be consecutively inserted like the numbering sequence of FIG. 4.

In order to make one segment received by the receiver into the known data like the example shown in FIG. 5B, one segment is divided into 52 bytes unit and the known data should be inserted in the same byte position by 52-byte unit like the example shown in FIG. 5A. In this case, an initialization byte needs to be placed at a beginning part of a known data sequence. Hence, once a place of the known data within the segment is determined, a place, where normal data ends and the known data begins in aspect of a data interleaver output end, is determined as the place of the initialization byte.

Once the places of the known data and the initialization byte are determined, it is able to determine a place of a non-systematic RS parity byte. In this case, parity bytes are placed to be outputted behind the initialization bytes in aspect of the data interleaver output. In particular, in aspect of one segment, since a sequence having a small numbering in FIG. 4 is firstly outputted from the data interleaver, the RS parity is placed to a number behind the sequence numbers of the initialization bytes.

For example of inserting the known data, in aspect of a data interleaver output configuration shown in FIG. 5B, if known data is inserted behind MPEG header in a first segment to reach the end of the segment, the MPEG header bytes in the second segment can be used a continuation of the known data because the MPEG header bytes for an enhanced data packet have a pre-determined value between a transmitter and a receiver.

FIGS. 6A to 6C show configurations of enhanced data packet groups according to the known data insertion of the present invention, respectively.

FIG. 6A shows a data configuration at an input end of the data interleaver 112 or 122 and FIG. 6B shows a data configuration at an output end of the data interleaver 112 or 122. And, FIG. 6C shows a data configuration result of output bytes of the data interleaver, in which the output bytes are converted to symbols by the trellis encoding unit 123 and are interleaved in a symbol domain.

In FIG. 6A, a small rectangle means one byte, one row means one enhanced data packet including 207 bytes, and 104 consecutive enhanced data packets configure one group. In the drawing, a 3-byte MPEG transport header byte excluded 0x47 sync byte is inserted by the E-VSB packet formatter 102, a known data place holder byte inserted by the E-VSB packet formatter 102, a 604 area indicates a non-systematic RS parity place holder or RS parity inserted by the RS encoder & non-systematic RS parity place holder inserter 111 or 121, a 605 area indicates enhanced data, and a 602 area indicates a known data place holder byte to be used in initializing the trellis encoder.

Meanwhile, in the drawing, a 606 or 607 area indicates enhanced data. The enhanced data in the 606 area is interleaved with main data prior to an enhanced data packet group by the data interleaver 112 or 122 and is then outputted. The enhanced data in the 607 area is interleaved with main data after the enhanced data packet group by the data interleaver 112 or 122 and is then outputted.

If the enhanced data packet group shown in FIG. 6A is interleaved by the data interleaver 112 or 122, it is outputted as shown in FIG. 6B.

In FIG. 6B, a white area indicates main data bytes before and after the enhanced data packet group. And, FIG. 6B shows that bytes of the enhanced data packet group are mixed with the main data bytes. The enhanced data packet group according to the present invention, as shown in FIG. 6B, is characterized in that a sequence of known data is periodically outputted from the output end of the data interleaver 112 or 122.

Meanwhile, FIG. 6C shows a data output of an area corresponding to middle 52 packets in FIG. 6B. In this case, the area is converted to symbols from bytes by the trellis encoding unit 123, encoded and then goes through the frame multiplexer 140. In particular, FIG. 6C shows a data configuration in a symbol domain.

One small rectangle in FIG. 6C means one symbol and one row indicates one data segment configured with 4 segment sync symbols and 828 (=207×4) data symbols.

An output of the data interleaver 122 is converted to symbol from byte via the trellis encoding unit 123, interleaved and trellis-encoded in a symbol domain and is then inputted to the frame multiplexer 140.

The frame multiplexer 140 attaches four segment sync symbols to each trellis-encoded input 828 symbols to configure a data segment having 832 symbols. In FIG. 6C, a 608 area indicates segment sync symbols inserted by the frame multiplexer 140.

A 12-byte 608′ area in front of each known data sequence repeated each four segments in FIG. 6B indicates a byte to be used in initializing twelve trellis encoders and is converted to 48 symbols by the trellis encoding unit 123 to have the configuration shown in FIG. 6C. Since two symbols are needed to initialize each of the trellis encoders and since there are total twelve trellis encoders, total 24 symbols are used for the trellis initialization among the 48 symbols in a manner of assigning two initial symbols to each of the trellis encoders. So, the rest 24 symbols can be used as known data symbols.

Meanwhile, an area enclosed by a black rim is an area in which a same known data symbol sequence is repetitively inserted with uniform interval. In this case, the interval for inserting the known data symbol sequence preferably corresponds to an integer multiplication of a data segment length. This is to enable a segment sync symbol inserted by the frame multiplexer 140 to be inserted in the same position within the known data sequence so that the segment sync symbol is used as a portion of the known data sequence.

Although FIGS. 6A to 6C show the embodiments of configuring one group with 104 enhanced data packets, the number of enhanced packets configuring one group can be arbitrarily chosen. Yet, since the data interleaver 112 or 122 interleaves data by 52-packet unit, the number is preferably chosen to be an integer multiple of 52 packets.

In FIG. 6C, the known data symbol sequence is repetitively inserted with 4-segment interval. FIGS. 7A to 7C show a case that the known data symbol sequence is repetitively inserted with 5-segment interval. FIGS. 8A to 8C show a case that the known data symbol sequence is repetitively inserted with 8-segment interval.

Thus, the enhanced data packet according to the present invention can be configured to include the enhanced data carrying information and the known data inserted for reception performance enhancement.

In this case, it is needed to initialize one or more memories of a trellis encoder at a beginning part of a known data sequence with reference to an output sequence of the data interleaver. If the initialization byte is located within a data segment, non-systematic RS parity bytes should be placed to be outputted behind the initialization byte in an output sequence of the data interleaver. Namely, if there is no initialization byte in the data segment, a place of the non-systematic RS parity byte can be randomly chosen.

By considering the relation between the position of the known data place holder for initializing the trellis encoder and the position of the non-systematic RS parity byte, the enhance data packet is configured in a manner that the E-VSB packet formatter 102 determines the known data place and that the RS parity place holder inserter 111 or 121 inserts the non-systematic RS parity place holder.

FIG. 9 is a block diagram of a digital broadcast receiving system according to one embodiment of the present invention. In particular, the digital broadcast receiving system receives data transmitted from the digital broadcast transmitting system shown in FIG. 1 and then recovers the received data into original data by demodulation and equalization.

Referring to FIG. 9, a digital broadcast receiving system according to one embodiment of the present invention includes a tuner 701, a demodulator 702, a known data detector & generator 704, a Viterbi decoder 705, a data deinterleaver 706, an RS decoder & non-systematic RS parity remover 707 and a derandomizer 708.

And, the digital broadcast receiving system includes a main data packet remover 709, an E-VSB packet deformatter 710 and an E-VSB data processor 711.

The tuner 701 tunes to down-convert a frequency of a specific channel and then outputs it to the demodulator 702 and the known data detector & generator 704.

The demodulator 702 performs carrier recovery and timing recovery on the tuned channel frequency so that converts the input signal to a baseband signal and then outputs the baseband signal to the equalizer 703 and the known data detector & generator 704.

The equalizer 703 compensates distortion on channel included in the demodulated signal and then outputs the compensated signal to the Viterbi decoder 705.

In this case, the known data detector & generator 704 detects a known data symbol sequence inserted by a transmitting side from input/output data of the demodulator 702, i.e., data before or after the demodulation and then outputs a generated symbol sequence of the known data to the demodulator 702 and the equalizer 703.

The demodulator 702 is able to enhance demodulation performance using the known data symbol sequence in timing or carrier recovery. Likewise, the equalizer 703 is able to enhance equalization performance using the known data.

The Viterbi decoder 705 converts main data symbol and enhanced data symbol outputted from the equalizer 703 to bytes by Viterbi decoding and then outputs the converted bytes to the deinterleaver 706.

The deinterleaver 706 performs a reverse process of the data interleaver of the transmitting side and then outputs a corresponding signal to the RS decoder & non-systematic RS parity remover 707.

The RS decoder and non-systematic RS parity remover 707 performs systematic RS decoding in case that the received packet is a main data packet. If the received packet is an enhanced data packet, the RS decoder & non-systematic RS parity remover 707 removes non-systematic RS parity byte from the packet and then outputs it to the derandomizer 708.

The derandomizer 708 performs a reverse process of a randomizer on an output of the RS decoder and non-systematic RS parity remover 707, inserts MPEG sync byte in a front of each packet and then outputs it by 188-byte packet unit.

An output of the derandomizer 708 is outputted to both a main MPEG decoder (not shown in the drawing) and the main data packet remover 709.

The main MPEG decoder performs decoding on a packet corresponding to main MPEG only. This is because the enhanced data packet, which has null-packet PID or PID with the main data stream, is ignored by the main MPEG decoder instead of being used for the decoding.

Meanwhile, the main data packet remover 709 removes 188-byte main data packet from the output of the derandomizer 708 and then outputs it to the E-VSB packet deformatter 710.

The E-VSB packet deformatter 710 removes 4-byte MPEG header having been inserted in the enhanced data packet by the E-VSB packet formatter of the transmitting side from the enhanced data packet. Also the E-VSB packet deformatter 711 removes place holders for the known data from the 184-byte enhanced data packet and then outputs it to the E-VSB data processor 711.

And, the E-VSB data processor 711 finally outputs enhanced data by performing a reverse process of the E-VSB pre-processor 101 of the transmitting side on an output of the E-VSB packet deformatter 710.

Accordingly, the present invention provides the following effects or advantages.

First of all, the present invention is strong against error in transmitting additional data via a channel. And, the present invention is compatible with a conventional VSB receiver. Moreover, the present invention enables an errorless reception of additional data on a channel having ghost and noise worse than those of the related art VSB system.

Secondly, the present invention transmits known data inserted in a specific place of a data area, thereby enhancing reception performance of a receiving system having considerable channel variations.

In particular, the present invention can move a parity place by performing non-systematic RS encoding on enhanced data packet including known data, thereby inserting a consecutively long known data sequence and raising a degree of freedom of an insertion place. In particular, it is possible to insert known data in a parity area of systematic RS encoding and to expand an area where initialization bytes can be inserted.

Finally, the present invention is effectively applicable to a portable or mobile receiver requiring robustness against noise with considerable channel variations.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. 

1-36. (canceled)
 37. A transmitter for transmitting main and enhanced data, the transmitter comprising: a first encoder for encoding the enhanced data for forward error correction (FEC); a packet formatter for forming enhanced data packets including the encoded enhanced data and a plurality of known data sequences; a second encoder for Reed Solomon (RS)-coding data in the enhanced data packets, the second encoder adding non-systematic RS parity data to the enhanced data packets; a data interleaver for interleaving the RS-coded data; a trellis encoder for trellis-encoding data in the interleaved data, wherein the trellis encoder includes a plurality of memories that are initialized by initialization data at a start of each of the plurality of known data sequences; a non-systematic RS encoder for generating new parity data based on the initialization data and outputting the generated new parity data; and a first multiplexer for selecting the interleaved data output from the data interleaver or the generated new parity data output from the non-systematic RS encoder, and providing the selected data to the trellis encoder.
 38. The transmitter of claim 37, further comprising: a second multiplexer for multiplexing the trellis-encoded data with frame sync data and segment sync data.
 39. The transmitter of claim 37, further comprising: a pilot inserter for inserting pilot signals into an output signal of the second multiplexer; a modulator for converting the output signal into an intermediate frequency (IF) signal; and an RF converter for converting the IF signal into an RF signal for transmission.
 40. The transmitter of claim 37, wherein the plurality of known data sequences include regularly spaced known data sequences.
 41. The transmitter of claim 37, wherein the initialization data are previous values stored in the plurality of memories that cause current values stored in the plurality of memories to be set to zero.
 42. A method of transmitting enhanced data in a transmitter, the method comprising: encoding, at a first encoder, the enhanced data for forward error correction (FEC); forming, at a packet formatter, enhanced data packets including the encoded enhanced data and a plurality of known data sequences; Reed-Solomon (RS) coding, at a second encoder, data in the enhanced data packets by adding non-systematic RS parity data to the enhanced data packets; interleaving, at a data interleaver, the RS-coded data; trellis-encoding, at a trellis encoder, data in the interleaved data, wherein the trellis encoder includes a plurality of memories that are initialized by initialization data at a start of each of the plurality of known data sequences; generating, at a non-systematic RS encoder, new parity data based on the initialization data and outputting the generated new parity data; and selecting, at a first multiplexer, the interleaved data output from the data interleaver or the generated new parity data output from the non-systematic RS encoder, and providing either the selected interleaved data or the generated new parity data to the trellis encoder.
 43. The method of claim 42, further comprising: multiplexing, at a second multiplexer, the trellis-encoded data with frame sync data and segment sync data.
 44. The method of claim 43, further comprising: inserting pilot signals into an output signal of the second multiplexer; converting the output signal into an intermediate frequency (IF) signal; and converting the IF signal into an RF signal for transmission.
 45. The method of claim 42, wherein the plurality of known data sequences include regularly spaced known data sequences.
 46. The method of claim 42, wherein the initialization data are previous values stored in the plurality of memories that cause current values stored in the plurality of memories to be set to zero. 